(1) Field of the Invention
The present invention relates to a fabrication process used to create semiconductor devices, and more specifically to a process used to form a butted contact, used to connect a gate structure, to an active device region of a memory device.
(2) Description of Prior Art
The butted contact concept, connecting a gate structure to an active device region, has been used in semiconductor memory devices, to increase device density by reducing the amount of area needed for contact purposes. The use of the butted contact, in SRAM designs, incorporate the butted contact, opened to a region overlying a insulator passivated gate structure, and an active device region, such as the source and drain region of SRAM transfer gate transistors. Therefore to complete the opening of the butted contact hole, a region of the insulator, overlying the gate structure, has to be removed. The removal of this insulator, on the underlying gate structure, now exposing an unpassivated region, or an extension of, the gate structure, can also result in unwanted gouging of adjacent isolation regions, such as insulator filled, shallow trenches, (STI). The gouging, or removal of insulator from STI regions, can result in unwanted exposure of specific regions of the semiconductor substrate, and when subsequently overlaid with contact metallization, can result in a deleterious leakage or shorting phenomena.
This invention will describe a novel process for forming a butted contact, allowing the desired simultaneous connection between a gate structure, and an active device region, however without the vulnerability of exposing unwanted semiconductor surfaces. An organic layer, such as polyimides, or layers used as bottom anti-reflective coatings, (BARC), is applied prior to applying an overlying photoresist layer. The BARC layer, or organic layer, thicker in the spaces between gate structures, than in regions overlying the gate structures, allow the removal of insulator from the gate structure, while still protecting active device regions between gate structures, during the reactive ion etch, (RIE), butt contact opening. In addition the RIE selectivity between the insulator layer, being removed from the top surface of the gate structure, and the organic layer, or the faster removal rate of insulator layer compared to organic layer, offers additional insurance against unwanted attack of semiconductor regions. Prior art, such as Hsue et al, in U.S. Pat. No. 5,521,113, show a process used to create a butted contact, however the use of an organic layer, used in this invention, to protect semiconductor regions, from unwanted exposure to the butt contact opening procedure, is not shown in that prior art.